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full/low speed 5 kv usb digital isolator adum4160 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may resul t from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2009 - 2010 analog devices, inc. all rights reserved. features usb 2.0 compatible low and full speed data rate: 1.5 mbps and 12 mbps bidirectional communication 4. 5 v to 5 .5 v v bus operation 7 ma maximum up stream supply current @ 1.5 mbps 8 ma maximum up stream supply current @ 12 mbps 2.3 ma maximum up stre am idle current upstream short - circuit protection class 3a contact esd performance per ansi/esd stm5.1 - 2007 high temperature operation: 105 c high common - mode transient immunity: >25 kv/ s 16- lead soic wide - body package version 16- lead soic wide body enhanced creepage version rohs compliant safety and regulatory approvals (ri - 16 package) ul recognition: 50 00 v rms for 1 minute per ul 1577 csa c omponent acceptance notice #5a iec 60601 - 1: 250 v rms (reinforced) iec 60950 - 1: 400 v rms (reinforced) vde c ertificate of c onformity din v vde v 0884 - 10 (vde v 0884 - 10):2006 - 12 v iorm = 846 v peak applications usb peri ph eral isolation isolated usb h ub medi cal applications general description the adum4160 1 is a usb port isolator, based on an a log devices, inc., i coupler? technology. combining high speed cmos and monolithic air core transformer technology, these isolation components provide outstanding perform ance chara c teristics and are easi ly integrated with low and full speed usb - compatible peripheral devices. functional block dia gram 1 v bus1 2 gnd 1 3 v dd1 7 ud+ 8 gnd 1 4 pden 16 v bus2 15 gnd 2 14 v dd2 11 dd? 10 dd+ 9 gnd 2 13 spd 12 pin 5 spu 6 ud? reg pu logic reg pd logic 08171-001 figure 1. many microcontrollers implement usb so that it presents only the d+ and d ? lines to external pins. this is desirable in many cases because it minimizes external components and simplifies the design; however, this presents particular challenges when isolation is required. usb lines must automatically switch between actively driving d+/d ?, receiving data, and allowing external resistors to set the idle state of the bus. t he adum4160 provides mechanism s for detecting the d irection of data flow and control over the state of the output buffers. data direction is determined on a packet - by - packet basis . the adum4160 uses the edge detection based i coupler tech - nology in conjunction with internal logic to implement a transparent , easily configured , up stream facing port isolator . isolating an upstream facing port provides several advantages in simpl icity , power management , and robust operation. the isolator has propagation delay comparable to that of a standard hub and cable . it operate s with the bus voltage on either side ranging from 4. 5 v to 5.5 v, allowing connection directly to v bus b y internal ly regulating the voltage to the signaling level . the adum 4160 provides isolated control of the pull - up resistor to allow the peripheral to control connection timing . the device has a low idle current ; so a suspend mode is not required . a 2.5 kv version, t he adum3160 , is also available. 1 protected by u.s. patents 5,952,849; 6,873,065; 7,075,329.
adum4160 rev. c | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics ............................................................. 3 package characteristics ............................................................... 4 regulatory information ............................................................... 4 insulation and safety-related specifications ............................ 5 din v vde v 0884-10 (vde v 0884-10) insulation characteristics .............................................................................. 5 recommended operating conditions ...................................... 6 absolute maximum ratings ............................................................ 7 esd caution...................................................................................7 pin configuration and function descriptions ..............................8 applications information .............................................................. 10 functional description .............................................................. 10 product usage ............................................................................. 10 compatibility of upstream applications ................................ 10 power supply options ............................................................... 11 printed circuit board layout (pcb) ....................................... 11 dc correctness and magnetic field immunity ..................... 11 insulation lifetime ..................................................................... 12 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 14 revision history 10/10rev. b to rev. c changes to features and general description section ............... 1 changes to endnote 3 in table 1 and table 3 ............................... 4 changes to table 4 ............................................................................ 5 changes to table 7 and table 8 ....................................................... 7 updated outline dimensions ....................................................... 14 changes to ordering guide .......................................................... 14 8/10rev. a to rev. b change to data sheet title .............................................................. 1 changes to features section............................................................ 1 changes to applications section .................................................... 1 changes to general description section ...................................... 1 changes to table 3 ............................................................................ 4 9/09rev. 0 to rev. a added usb logo, reformatted page 1 .......................................... 1 7/09revision 0: initial version
adum4160 rev. c | page 3 of 16 specifications electrical character istics 4. 5 v v bus 1 5.5 v, 4. 5 v v bus 2 5.5 v; 3. 1 v v dd1 3. 6 v, 3 . 1 v v dd2 3.6 v ; all min imum /max imum specifications apply over the entire recommended operation range, unless othe r wise noted; all typical specifications are at t a = 25c, v dd1 = v dd2 = 3.3 v. each voltage is relative to its respective ground. table 1 . parameter symbol min typ max unit test conditions dc specifications total supply current 1 1.5 mbps v dd1 or v bus1 supply current i dd1 (l) 5 7 ma 750 k hz logic signal rate c l = 450 pf v dd2 or v bus2 supply current i dd2 (l ) 5 7 ma 750 khz logic signal rate c l = 450 pf 1 2 mbps v dd1 or v bus1 supply current i dd1 ( f) 6 8 ma 6 mhz logic signal rate c l = 50 pf v dd2 or v bus2 supply current i dd 2 ( f) 6 8 ma 6 mhz logic signal rate c l = 50 pf idle current v dd1 or v bus1 idle current i dd1 (i) 1.7 2.3 ma input currents i dd? , i dd+ , i ud+ , i ud ? , i spd , i pin , i spu , i pden ?1 +0. 1 +1 a 0 v v dd - , v dd+ , v ud+ ,v ud ? , v spd , v pin , v spu , v pden 3. 0 s ingle - ended logic high input threshold v ih 2.0 v single - ended logic low input threshold v il 0.8 v single - ended input hysteresis v hst 0.4 v differential input sensitivity v di 0.2 v |v xd+ ? v xd ? | logic high output voltages v oh 2.8 3.6 v r l = 15 k ?, v l = 0 v logic low output voltages v ol 0 0. 3 v r l = 1.5 k ?, v l = 3.6 v v dd1 and v dd2 supply under v oltage lockout v uvlo 2. 4 3. 1 v v bus1 supply under v oltage lockout v uvlob1 3.5 4.35 v v bus2 supply unde rv oltage lockout v uvlob2 3.5 4.4 v transceiver capacitance c in 10 pf ud+, ud ?, dd+, dd? to ground capacitance matching 10 % full speed driver impedance z outh 4 20 ? impedance matching 10 % switching specifications, i/o pins low speed low speed data rate 1.5 mbps c l = 50 pf propagation delay 2 t phll , t plhl 325 ns c l = 50 pf , spd = spu = low v dd1 , v dd2 = 3.3 v side 1 output rise/fall time (10% to 90%) low speed t rl /t fl 75 300 ns c l = 450 pf spd = spu = low v dd1 , v dd2 = 3.3 v low speed differential jitter, nex t transition |t ljn | 45 ns c l = 50 pf low speed differential jitter, paired transition |t ljp | 15 ns c l = 50 pf switching specifications, i/o pins full speed full speed data rate 12 mbps c l = 50 pf propagation delay 2 t phlf , t plhf 20 60 70 ns c l = 50 pf spd = spu = high, v dd1 , v dd2 = 3.3 v output rise/fall time (10% to 90%) full speed t rf /t ff 4 20 ns c l = 50 pf spd = spu = high, v dd1 , v dd2 = 3.3 v full speed differential jitter, next transiti on |t fjn | 3 ns c l = 50 pf full speed differential jitter, paired transition |t fjp | 1 ns c l = 50 pf
adum4160 rev. c | page 4 of 16 parameter symbol min typ max unit test conditions for all operating modes common - mode transient immunity at logic high output 3 |cm h | 25 35 kv/s v ud+ , v ud ? , v dd+ , v dd? = v dd1 or v dd2 , v cm = 1000 v, transient magnitude = 800 v at logic low output 3 |cm l | 25 35 kv/s v ud+ , v ud ? , v dd+ , v dd? = 0 v, v cm = 1000 v, transient magnitude = 800 v 1 the supply current values for the device running at a fixed continuous data rate at 50% duty cycle alternating j and k states. supply current values are specified with usb - compliant load present. 2 propagation delay of the low speed dd+ to ud+ or dd? to ud? in either signal direction is measured from the 50% level of the rising or falling edge , to the 50% le vel of the rising or falling edge of the corresponding output signal. 3 cm h is the maximum common - mode voltage slew rate that can be sustained w hile maintaining v o > 0.8 v ddx . cm l is the maximum common - mode voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges. the tra n sient magnitude is t he range over which the common mode is slewed. package characterist ics table 2. parameter symbol min typ max unit test conditions resistance (input to output) 1 r i-o 10 12 ? capacitance (input to output) 1 c i-o 2.2 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction - to - ambient thermal resistance ja 45 c/w thermocouple located at center of package underside 1 device is considered a 2 - terminal device; pin 1, pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, and pin 8 are shorted together and pin 9, pin 10, pin 11, pin 12, pin 13, pin 14, pin 15, and pin 16 are shorted tog ether. 2 input capacitance is from any input data pin to ground. regulatory informati on the adum 4160 is approved by the organizations listed in table 3 . refer to table 8 and the insulation lifetime section for details regarding recommended maximum working voltages for specific cross - isolation waveforms and insulation levels. table 3. ul csa vde recognized und er 1577 component recogn i tion program 1 approved under csa component acce p tance notice #5a certified according to din v vde v 0884 - 10 (vde v 0884- 10):2006 - 12 2 single protection 5000 v rms isolation vol t age basic insulation per csa 60950 -1- 03 and iec 6095 0- 1, 600 v rms (848 v peak) maximum working voltage reinforced insulation per csa 60950 -1- 03 and iec 60950 - 1, 380 v rms (537 v peak) maximum working vol t age, rw - 16 package. reinforced insulation per csa 60950 -1- 03 and iec 60950 - 1, 400 v rms (565 v peak) maximum working vol t age, ri - 16 package . reinforced insulation, 846 v peak reinforced insulation per iec 60601 - 1 125 v rms (176 v peak) maximum working voltage, rw - 16 package. reinforced insulation per iec 60601 - 1 250 v rms (353 v peak) maximum working vo ltage, ri - 16 package. file e214100 file 205078 file 2471900 - 4880 - 0001 1 in accordance with ul 1577, each adum4160 is proof tested by applying an insulation test voltage 6 000 v rms for 1 sec (current leakage detection limit = 10 a). 2 in accordance with din v vde v 0884 - 10 , each adum4160 is proof tested by applying an insulation test voltage 1050 v peak for 1 sec (partial discharge detection limit = 5 pc). the * marking branded on the component designates din v vde v 0884 - 10 approval.
adum4160 rev. c | page 5 of 16 insulation and safet y - related specificatio ns table 4 . parameter symbol value unit conditions rated dielectric insulation voltage 5 0 00 v rms 1 minute durati on minimum external air gap (clearance) l(i01) 8.0 min mm measured from input terminals to output terminals, shortest distance through air minimum external tracking (creepage) rw - 16 package l(i02) 7.7 min mm measured from input terminals to output termin als, shortest distance path along body minimum external tracking (creepage) ri - 16 package l(i02) 8.5 min mm measured from input terminals to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.017 min mm insul ation distance through insulation tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1) din v vde v 0884 - 10 (vde v 0884 - 10) insulation character istics these isolators are suitable for reinforced electrical isolation only within the safety limit data. maintenance of the safety data is ensured by prote c tive circuits. the * marking on packages denotes din v vde v 0884 - 10 approval. table 5 . description conditions symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classification 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 846 v peak input - to - output test voltage, method b 1 v iorm 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc v pr 1 59 0 v peak input - to - output test voltage, method a v iorm 1.6 = v pr , t m = 60 sec, partial discharge < 5 pc v pr after e nvironmental tests subgroup 1 1375 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pr , t m = 60 sec, partial discharge < 5 pc 1018 v peak highest allowable overvoltage transient overvoltage, t tr = 10 seconds v tr 6 000 v p eak safety - limiting values maximum value allowed in the event of a failure ( see figure 2 ) case temperature t s 150 c side 1 + side 2 current i s1 550 ma insulation resistance at t s v io = 500 v r s >10 9 ? 0 100 200 300 400 500 600 0 50 100 150 200 ambient temperature (c) safe operating v dd1 current (ma) 08171-002 figure 2 . thermal derating curve, dependence of safety - limiting values with case temperature per din v vde v 0884 - 10
adum4160 rev. c | page 6 of 16 recommended operatin g conditions table 6 . parameter symbol min max unit operating temperature t a ?40 +105 c supply voltages 1 v bus 1 , v bus 2 3. 1 5.5 v input signal rise and fall times 1.0 ms 1 all voltages are relat ive to their respective ground. see the dc correctness and magnetic field immunity section for information on immunity to external ma g netic fields.
adum4160 rev. c | page 7 of 16 absolute maximum rat ings ambient temperature = 25c, unless otherwise noted. table 7. parameter rating storage temperature (t st ) ?65c to +150c ambient operating temperature (t a ) ?40c to +105c supply voltages (v bus 1 , v bus 2 , v dd1 , v dd2 ) 1 ?0.5 v to + 6.5 v upsream input voltage (v ud+ ,v ud ? , v spu ) 1 , 2 ?0.5 v to v dd1 + 0.5 v downstream i nput voltage (v dd+ , v dd? , v spd , v pin ) 1 , 2 ?0.5 v to v dd2 + 0.5 v average output current per pin 3 side 1 (i o1 ) ? 10 ma to +1 0 ma side 2 (i o2 ) ? 10 ma to + 10 ma common - mode transients 4 ?100 kv/s to +100 kv/s 1 all voltages are relative to their respective ground. 2 v ddi , v bus1 , and v dd2 , v bus2 refer to the supply voltages on the upstream and downstream sides of the coupler, respectively. 3 see figure 2 for maximum rated current values for various temperatures. 4 refers to common - mode transients across the insulation barrier. common - mode transients exceeding the absolute maximum ratings may cause latch - up or perm a nent damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 8 . maximum continuous working voltage 1 parameter max unit constraint ac voltage, bipolar waveform 565 v peak 50- year minimum lifetime ac voltage, unipolar waveform basic insulation 848 v peak maximum approved working voltage per iec 60950 -1 reinforced insulation 846 v peak maximum approved working voltage per vde 0884 -10 dc voltage basic insulation 848 v peak maximum approved working voltage per iec60950 -1 reinforced insulation 846 v peak maximum approved working voltage per vde 0884 -10 1 refers to continuous voltage magnitude imposed across the isolation barrier. see the insulation lifetime section for more details. esd caution
adum4160 rev. c | page 8 of 16 pin configuration an d function descripti ons v bus1 1 gnd 1 * 2 v dd1 3 pden 4 v bus2 16 gnd 2 * 15 v dd2 14 spd 13 spu 5 pin 12 ud? 6 dd? 11 ud+ 7 dd+ 10 gnd 1 * 8 gnd 2 * 9 adum4160 top view (not to scale) nc = no connect * pin 2 and pin 8 are internally connected, and connecting both to gnd 1 is recommended. pin 9 and pin 15 are internally connected, and connecting both to gnd 2 is recommended. 08171-003 figure 3 . pin configuration table 9 . pin function des criptions pin no. mnemonic direction description 1 v bus 1 power input power supply for side 1. where the is olator is powered by the usb bus voltage, 4.5 v to 5.5 v , connect v bus1 to the usb power bus. where the isolator is powered from a 3.3 v power supply , connect v bus1 to v dd1 and to the external 3.3 v power supply. bypass to gnd 1 is required. 2 gnd 1 return ground 1. ground reference for i solator side 1. 3 v dd1 power power supply for side 1. where the isolator is powered by the usb bus voltage, 4.5 v to 5.5 v, t he v ddi pin should be use d f or a bypass capacitor to gnd 1 . signal lines that may require pull up , such as pden and spu , should be tied to this pin. where the isolator is powered from a 3.3 v power supply, connect v bus1 to v dd1 and to the external 3.3 v power suppl y . bypass to gnd 1 is required . 4 pden i nput pul l - down enable . this pin is read when exiting reset. for standard operation, connect t his pin to v dd1 . when connected to gnd 1 whi le exiting from reset, the down stream pull - down resistors are d isconnected, allowing buffer impedance measurements. 5 spu i nput speed select upstream buffer. active high logic input. s elects f ull speed slew rate , timing , and logic conventions when spu is high , and low speed slew rate, timing , and logic conventions wh en spu is tied low . this input must be set high via connection to v dd1 or set low via connection to gnd 1 and must match p in 13. 6 ud ? i/o upstream d ?. 7 ud+ i/o upstream d+ . 8 gnd 1 return ground 1. ground reference for i solator side 1. 9 gnd 2 return ground 2. ground reference for i solator side 2. 10 dd+ i/o down stream d+ . 11 dd? i/o down stream d ? . 12 pin i nput upstream pull - up e n able. pin controls t he power connection to the pull - up for the upstream port. it can be tied to v dd2 for operation on power - up, or tied to an external control signal for application s requiring delayed enumeration. 13 spd i nput speed select down s tream buf fer. active high logic input. selects full speed slew rate, timing , and logic conventions when spd is high, and low speed slew rate, timing , and logic conventions when spd is tied low. this input must be set high via connection to v dd2 or low via connectio n to gnd 2 , and must match p in 5 . 14 v dd2 power power supply for side 2. where the isolator is powered by the usb bus voltage, 4.5 v to 5.5 v, t he v dd 2 pin should be used for a bypass capacitor to gnd 2 . signal lines that may require pull -up , such as spd , c an be tied to this pin. where the isolator is powered from a 3.3 v power supply, connect v bus2 to v dd2 and to the external 3.3 v power supply. bypass to gnd 2 is required. 15 gnd 2 return ground 2. ground reference for i solator side 2. 16 v bus2 power inp ut power supply for side 2. where the isolator is powered by the usb bus voltage, 4.5 v to 5.5 v, connect v bus2 to the usb power bus. where the isolator is powered from a 3.3 v power supply, connect v bus2 to v dd2 and to the external 3.3 v power supply. bypas s to gnd 2 is required.
adum4160 rev. c | page 9 of 16 table 10 . truth table , control signals , and power (positive logic) 1 v spu input v bus1 , v dd1 state v ud+ , v ud ? state v spd input v bus2 , v dd2 state v dd+ , v dd? state v pin input notes h powered active h powered active h input and output logic set for full speed logic convention and timing. l powered active l powered active h input and output logic set for low spe ed logic convention and timing. l powered active h powered active h not allowed : v spu and v spd must be set to the same value. usb host detects communications error. h powered active l powered active h n ot allowed : v spu and v spd must be set to the same v alue. usb host detects communications error. x powered z x powered z l upstream side 1 presents a disconnected state to the usb cable. x unpowered x x powered z x when power is not present on v dd1 , the downstream data output drivers revert to high - z with in 32 bit times. the downstream side initializes in high - z state. x powered z x unpowered x x when power is not present on the v dd2 , the upstream side disconnects the pull - up and disables the upstream drivers within 32 bit times. 1 h represents logic high input or output, l represents logic low input or out put, x represents the dont care logic input or output, and z represents the high impedance output state.
adum4160 rev. c | page 10 of 16 application s informati on functional descripti on usb isolation in the d+/d ? lines is challenging for several reasons. fi r st, access to the output enable signals is normally required to control a transceiver . some level of intelligence must be built into the isolator to interpret the data stream and determine when to enable and d isable its upstream and down - stream output buffers. second , the signal must be faithfully reconstructed on the output side of the coupler while retaining precise timing and not passing transient states such as invalid se0 and se1 states. in addition, the p art must meet the low power requirements of the s uspend mode. the i coupler technology is based on edge detection, and , therefore , lends itself well to the usb application. the flow of data through the device is accomplished by mon itoring the inputs for act ivity and setting the direction for data transfer based on a transition from the i dle (j) state. when data direction is established, data is transfer red until either an end - of - packet (eop) or a sufficiently long idle sta t e is encountered. at this point, t he coupler disables its output buffers and monitors its inputs for the next activity during the data transfers, the input side of the coupler holds its output bu ffers disabled. the output side enables its output buffers and disables edge detection from th e input buffers. this allows the data to flow in one directio n without wrapping ba ck through the coupler making the i coupler latch . l o gic is included to eliminate any artifacts due to different input thresholds of the differential and single - ended buffers. the input s tate is transferred across the isolation barrier as one of three valid states, j , k, or se0. the signal is reconstructed at the output side with a fixed time delay from the input side differential input. the i coupler does not have a special sus pend mode, nor does it need one because its power supply current is below the suspend current limit of 2.5 ma when the usb bus is idle. the ad u m4160 is designed to interface with an upstream facing low/full s peed usb port by isolating the d+/d ? lines. an upstream facing port supports only one speed of operation , thus, the speed related parameters, j/k logic levels , and d+/d ? slew rate are set to match the speed of the upstream facing peripheral port (see table 10) . a control line o n the downstream side of the adum4160 activates a pull - up resistor integrated into the upstream side . thi s allow s the down strea m port to control w hen the upstream port attaches to the usb bus. the pin can be tied to the peripheral pull - up, a control line, or the v dd2 pin , depending on when the initial bus connect is to be performed. product us age the adum4160 is designed to be integrated into a usb peripheral with an upstream facing usb port as shown in figure 4 . the key design po ints are: 1. the usb host provides power for the upstream side of the adum4160 through the cable. 2. the peripheral supply provides power to the downstream side of the adum4160 3. the dd+/dd ? lines of the isolator interface with the peripheral controller , and the u d+/ u d ? lines of the isolator connect to the cable or host . 4. peripheral devices have a fixed data rate that is set at design time. the adum4160 has configuration pins , spu and spd , that determine the buffer speed and l ogic convention for each side. these mu st be set identically and match the desired peripheral speed. 5. usb enumeration begins when either the u d+ or u d ? line is pulled high at the peripheral end of the usb cable , which is the upstream side of the adum4160 . control of the timing of this event is p rovided by the pin input on the downstream side of the coupler. 6. p ull - u p and p ull - down resistors are implemented inside the coupler. only external series resistors and bypass capacitors are required for operation. usb host adum4160 v bus1 v bus2 dd+ dd? gnd 1 dd+ 3.3v v dd2 dd? pin micro- controller power supply peripheral 08171-004 figure 4. typica l application other than the delayed application of pull - up resistors, the adum4160 is transparent to usb traffic, and no modifications to the peripheral design are required to provide isola tion . the isolator adds propagation delay to the signals comparabl e to a hub and cable . i solate d peripherals must be treated as if there w ere a built - in hub when determining the maximum number of hubs in a data chain. hubs can be isolat ed like any other peripheral. isolated hubs can be created by placing an adum4160 on th e upstream port of a hub chip. th is configuration can be made compliant if counted as two hub delays. the hub chip allows the adum4160 to operate at full speed yet maintain s compatibility with low speed devices. compatibility of u pstream a pplications the adum4160 is designed specifically f or isolating a usb peripheral. however, the chip does have two usb interfaces that meet the electrical requir ements for driving usb cables. this opens the possibility of implementing isolation in down stream usb ports suc h as isolated cables, which have generic connections to both upstream and downstream devices, as well as isolating host ports.
adum4160 rev. c | page 11 of 16 in a fully compliant application , a downstream facing port must be able to detect whether a peripheral is low speed or full spee d based on the application of the up stream pull - up. the buffers and logic conventi on s must adjust to match the requested speed . b e cause the adum4160 sets its speed by hard wiring pins, the part cannot adjust to different peripherals on the fly. the practi cal result of using the adum4160 in a host port is that the port work s at a single speed. this behavior is acceptable in embedded host applications; h owever, this type of interface is not fully compliant as a general - purpose usb port. isolated cable applic atio ns have a similar issue. the cable operate s at the preset speed only ; therefore, treat cable assemblies as custom applications, not general - purpose isolated cables. power suppl y options in most usb transceivers, 3.3 v is derived from the 5 v usb bus t hroug h an ldo regulator. the adum4160 includes internal ldo regulator s on both the upstream and downstream sides . the output of the ldo is available on the v dd1 and v dd2 pins . in some c ase s , especially on the peripheral side of the isolation , there may not be a 5 v power supply available. t he adum4160 has the ability to bypass the regulator and run on a 3 .3 v supply directly . two power pins are present on each side, v busx and v ddx . if 5 v is supplied to v busx , an internal regulat or creates 3.3 v to power t he xd+ and xd ? drivers . v ddx provides external access to the 3.3 v supply to allow external bypass as well as bias for external pull - ups . if only 3.3 v is available, it can be supplied to both v busx and v ddx . this disables the regulator and powers the coupler directly from the 3.3 v supply. figure 5 shows how to configure a typical application when the upstream side of the coupler receives power directly from the usb bus and the downstream side i s receiving 3.3 v from the peripheral power supply . the downstream side can run from a 5v v bus2 power supply as well. it can be connected in the same man ne r as v bus1 as shown in figure 5 , if needed. p rinted c ircuit board layout (pcb) the adum4160 digital isolator requires no exte rnal interface circuitry for the logic interfaces. for full speed operation , t he d+ and d ? line on each side of the device require s a 24 ? 1% series termination resistor. these resistors are not required for low speed applications. power supply bypassing is required at the input and output supply pins ( figure 5 ). install b ypass capacitors between v busx and v ddx on each side of the chip . the capacitor value should have a value of 0.1 f and be of a low esr type . the total lead le ngth between both ends of the capacitor and the power supply pin should not exceed 10 mm . bypas s ing between pin 2 and pin 8 and between pin 9 and pin 1 5 should also be considered, unless the ground pair on each package side is connected close to the packag e. v bus1 gnd 1 v dd1 pden spu ud? ud+ gnd 1 v bus2 gnd 2 v dd2 spd pin dd? dd+ gnd 2 adum4160 v bus1 = 5.0v input v dd1 = 3.3v output v bus2 = 3.3v input v dd2 = 3.3v input 08171-005 figure 5 . recommended printed circuit board layout in applications involving high common - mode transients, it is important to minimize board coupling across the isol a tion barrier . furthermore, design the board layout such that any coupling that does occur equally a f fects all pins on a given component side. failure to ensure this c an cause voltage differentials between pins exceeding the absolute maximum ratings of the device , thereby leading to latch - up or permanent damage. dc c orrectness and magne tic field imm u nity positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the tran s former. the decoder is bistable and is, therefore, either set or reset by the pulses, i ndicating input logic transitions. in the absence of logic transitions at the input for more than about 12 usb bit times , a per i odic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. if the decode r r e ceives no internal pulses for more than about 36 u sb bit times , the input side is a s sumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see table 10 ) by the watchdog timer ci rcuit. the limitation on the magnetic field immunity of the adum4160 is set by the condition in which induced voltage in the receiving
adum4160 rev. c | page 12 of 16 coil of the transformer is sufficiently large to either falsely set or reset the decoder. the following analysis defines the conditions under which this may occur. the 3 v operating condition of the adu m 4160 is examined because it represents the most susceptible mode of operation. the pulses at the transformer output have an amplitude greater than 1.0 v. the decoder has a s ensing threshold of about 0.5 v, thus establishing a 0.5 v margin in which induced voltages ar e tolerated. the voltage induced across the receiving coil is given by v = ( ? d / d t ) r n 2 ; n = 1, 2, , n where: is magnetic flux density (gauss). n is the number of turns in the receiving coil. r n is the radius of the n th turn in the receiving coil (cm). given the geometry of the receiving coil in the adu m4160 and an imposed r equirement that the induced voltage is , at most , 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated , as shown in figure 6 . magnetic field frequency (hz) maximum allowable magnetic flux density (kguass) 1k 0.001 100 100m 10 1 0.1 0.01 10k 100k 1m 10m 08171-006 figure 6 . maximum allowable external mag netic flux density for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 kgauss induces a vol t age of 0.25 v at the receiving coil. this is about 50% of the sen s ing threshold and does not cause a faulty output tran sition . s im i larly, if such an event occur s during a transmitted pulse (and i s of the worst - case polarity), it r educe s the r e ceived pulse from >1.0 v to 0.75 v still well above the 0.5 v sensing threshold of the decoder. t he preceding magnetic flux density values correspond to sp e cific current magnitudes at given distances from the adu m4160 trans - formers. figure 7 expresses these allowable current magnitudes as a function of frequency for selected di s tances. magnetic field frequency (hz) maximum allowable current (ka) 1000 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 08171-007 figure 7 . maximum allowable current for various current - to- adum4160 spacings as shown, the adu m4160 is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. for the 1 mhz example noted, a 0.5 ka current would n eed to be placed 5 mm away from the adum 4160 to affect the operation of the component . note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces c an in duce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. ta ke c are in the layout of such t races to avoid this possibility. insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insulation degradation is depend e nt on the characteristics of the voltage waveform applied across the insulation. in addition to the testing performed by the regulatory agencies, analog devices ca r ries o ut an extensive set of evaluations to determine the lif e time of the insulation structure within the adum 4160. a nalog devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. accele - ration factors for several operating conditions are determined. these factors allow calculation of t he time to failure at the actual working voltage. the values shown in table 8 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition, and the maximum csa/vde approved working vol - t ages. in many cases, the approved working voltage is higher th an 50 - year service life voltage. operation at these high working voltages can lead to shortened insulation li fe in some cases. the insulation lifetime of the adum 4160 depends on the voltage waveform type imposed across the isol a tion barrier. the i coupler
adum4160 rev. c | page 13 of 16 insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac , or dc. figure 8 , figure 9 , and figure 10 illustrate these different isolation voltage wav e forms. bipolar ac voltage is the most stringent environment. the goal of a 50 - ye ar operating lifetime under the ac bipolar condition determines the analog devices recommended maximum working voltage. in the case of unipolar ac or dc voltage, the stress on the insula - tion is sig nificantly lower. this allows operation at higher working voltages and still achiev es a 50 - year service life. the working voltages listed in table 8 can be applied while maintaining the 50- year minimum lifeti me , provided that the voltage conforms to either the unipolar ac or dc voltage cases. treat a ny cross insulation voltage waveform that does not conf orm to figure 9 or figure 10 a s a bipolar ac waveform and limit its peak voltage to the 50- year lifetime voltage value l isted in table 8 . note that the voltage presented in figure 9 is shown as sinu - soidal for illustration purposes only. it is meant to represent any voltage waveform varying between 0 v and some limiting value. the limiting value can be positive or negative, but the voltage cannot cross 0 v. 0v rated peak voltage 08171-008 figure 8 . bipolar ac waveform 0v rated peak voltage 08171-009 figure 9 . unipolar ac waveform 0v rated peak voltage 08171-010 figure 10 . dc waveform
adum4160 rev. c | page 14 of 16 outline dimensions controlling dimensions are in millimeters; inch dimensions (in p arentheses) are rounded-off millimeter equi v alents for reference on l y and are not appropri a te for use in design. compliant t o jedec s t andards ms-013- aa 032707-b 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0 1 18) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) coplanarit y 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) sea ting plane 8 0 16 9 8 1 1.27 (0.0500) bsc figure 11 . 16 - lead standard small outline package [soic_w] wide body (rw - 16) dimension shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in p arentheses) are rounded-off millimeter equiv alents for reference onl y and are not appropria te for use in design. compliant t o jedec st andards ms-013-ac 10-12-2010-a 13.00 (0.51 18) 12.60 (0.4961) 0.30 (0.01 18) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) 8 0 1 6 9 8 1 1.27 (0.0500) bsc sea ting plane figure 12 . 16 - lead standard small outline package , with increased creepage [soic_i c ] wide body (ri - 16) dimension shown in millimeters and (inches) ordering guide model 1 , 2 number of inputs, v dd1 side number of inputs, v dd2 side maximum data rate (mbps) maximum propagation delay, 5 v (ns) m aximum jitter (ns) temperature range package description package option adum4160brwz 2 2 12 70 3 ?40c to +105c 16 - lead soic_w rw - 16 adum4160brwz - rl 2 2 12 70 3 ?40c to +105c 16 - lead soic_w rw - 16 adum4160briz 2 2 12 70 3 ?40c to +105c 16 - lead soic _i c ri - 16 adum4160briz - rl 2 2 12 70 3 ?40c to +105c 16 - lead soic_i c ri - 16 eval - adum4160ebz evaluation board 1 z = rohs compliant part. 2 for all devices listed, specific ations represent full speed buffer configuration.
adum4160 rev. c | page 15 of 16 notes
adum4160 rev. c | page 16 of 16 notes ? 2009 - 2010 analog devices, inc. all rights reserved. trademarks and re gistered trademarks are the property of their respective owners. d08171 - 0 - 10/10(c)

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